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Espressif Systems /ESP32-S3 /SPI0 /TIMING_CALI

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Interpret as TIMING_CALI

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIMING_CLK_ENA)TIMING_CLK_ENA 0 (TIMING_CALI)TIMING_CALI 0EXTRA_DUMMY_CYCLELEN

Description

SPI0 timing compensation register when accesses to flash.

Fields

TIMING_CLK_ENA

Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.
TIMING_CALI

Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.
EXTRA_DUMMY_CYCLELEN

Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data